1. Field of the Invention
This invention relates to a counter circuit for counting pulses. More particularly, the invention relates to a counter circuit for counting pulses inputted thereto asynchronously during a fixed period.
2. Description of the Related Art
A numerically controlled machine tool uses many servomechanisms. A numerically controlled servomechanism has an electric motor for directly driving a machine. The electric motor is provided with a pulse coder which outputs pulses proportional to the momentary rotational velocity of the electric motor. This information is fed back to a control circuit so that the velocity of the electric motor may be controlled. In a servomechanism of this kind, the momentary detection of velocity by the pulse coder is performed by counting, by means of a counter circuit, the number of pulses outputted by the pulse coder. It has recently become possible to control the entire servomechanism by a microcomputer and digitize the overall circuitry. This has made it possible to use the counter circuit not only in velocity detection but also in many other areas, such as in circuits that calculate the difference between a commanded rotational velocity and a present rotational velocity.
The above-described counter circuit, which is illustrated in FIG. 6, is known and used conventionally in the art. This circuit will now be described. A synchronous circuit 10 establishes synchronism between input pulses APup or APdn and outputs synchronous pulses SPup or SPdn. The output synchronous pulses SPup on SPdn are input into a control circuit. When pulses INTR having a fixed period are inputted to the control circuit 11 from a timing circuit 14, an enable pulse ENB is output which actuates an up-down counter 12, which counts the number of pulses UP or DN from the control circuit 11. In response to the next application of the pulse INTR, the results of counting performed by the counter 12 thus far are stored in a register 13, and the counter C is cleared.
FIG. 7 is a timing chart associated with this counter circuit, and FIGS. 8 and 9 are timing charts illustrating the various signal waveforms of FIG. 7 in enlarged form. If the input pulses SPup shown in FIG. 7 include a pulse P which operlaps the pulse INTR, there is the danger that mislatching will occur when the register 13 is latched. FIG. 8 is an enlargement of the timing chart illustrated in FIG. 7.
In order to eliminate this drawback, a timing signal I is generated in synchronism with the pulse INTR and shifted in phase with respect thereto so as not to overlap INTR, as shown in FIG. 9. If any pulse SPup which overlaps the pulse INTR, as shown by the pulse P in FIG. 7, is generated, this pulse will be shifted up to the position of the timing signal I, as illustrated in FIG. 9, and the enable pulse ENB will be formed which has a timing such that it will not overlap the pulse INTR, as shown in FIG. 9(e). This pulse is counted. Thus, control is performed in the control circuit 11 in such a manner that mislatching does not occur. When this control is carried out, clock pulses CLK are frequency-divided a number of times to form the timing signal I. Accordingly, a problem that arises is that the frequency of the input pulses APup, APdn cannot be increased.